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R8C/10 Group

Rev.1.20 Jan 27, 2006 page 43 of 180

REJ09B0019-0120

• Saving Registers

In the interrupt sequence, the FLG register and PC are saved to the stack.

At this time, the 4 high-order bits in the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG

Figure 10.6 shows the stack status before and after an interrupt request is accepted.

The other necessary registers must be saved in a program at the beginning of the interrupt routine.

The PUSHM instruction can save several registers in the register bank being currently used

(1)

with

a single instruction.

NOTES:

1. Selectable from registers R0, R1, R2, R3, A0, A1, SB, and FB.

Address

Content of previous stack

Stack

[SP]

SPvalue before

interrupt occurs

m – 1

m – 2

m – 3

m – 4

Stack status before interrupt request

is acknowledged

Stack status after interrupt request

is acknowledged

Content of previous stack

m + 1

MSB LSB

m – 1

m – 2

m – 3

m – 4

Address

FLG

Content of previous stack

Stack

FLG

[SP]

New SP value

Content of previous stack

m + 1

MSB LSB

Figure 10.6 Stack Status Before and After Acceptance of Interrupt Request

Figure 10.7 Operation of Saving Register

[

]

[

]

–

[

]

–

[

]

–

[

]

–

[

]

–

Sequence in which order

registers are saved

(

)

(

)

(

)

(

)

]

[

]

Stac

FLG

The registers are saved in four steps, 8 bits at a time. Figure 10.7 shows the operation of the saving

registers.

NOTES:

1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indi-

cated by the U flag. Otherwise, it is the ISP.

10.1 Interrupt Overview

1 2 ... 48 49 50 51 52 53 54 55 56 57 58 ... 198 199

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