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R8C/10 Group

Rev.1.20 Jan 27, 2006 page 40 of 180

REJ09B0019-0120

• I Flag

The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the

maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts.

• IR Bit

The IR bit is set to “1” (interrupt requested) when an interrupt request is generated. Then, when the

interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit

is cleared to “0” (= interrupt not requested).

The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.

Table 10.4 Interrupt Priority Levels Enabled

by IPL

Table 10.3 Settings of Interrupt Priority Levels

ILVL2 to ILVL0 bits

Interrupt priority

level

Priority

order

0002

0012

0102

0112

1002

1012

1102

1112

Level 0 (interrupt disabled)

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

Lowest

Highest

Enabled interrupt priority levels

Interrupt levels 1 and above are enabled

Interrupt levels 2 and above are enabled

Interrupt levels 3 and above are enabled

Interrupt levels 4 and above are enabled

Interrupt levels 5 and above are enabled

Interrupt levels 6 and above are enabled

Interrupt levels 7 and above are enabled

All maskable interrupts are disabled

IPL

000

0012

0102

0112

1002

1012

1102

1112

• ILVL2 to ILVL0 Bits and IPL

Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.

Table 10.3 shows the settings of interrupt priority levels and Table 10.4 shows the interrupt priority

levels enabled by the IPL.

The following are conditions under which an interrupt is accepted:

· I flag = 1

· IR bit = 1

· interrupt priority level > IPL

The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect

one another.

10.1 Interrupt Overview

1 2 ... 45 46 47 48 49 50 51 52 53 54 55 ... 198 199

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