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R8C/10 Group 13.1 Clock Synchronous Serial I/O Mode

Rev.1.20 Jan 27, 2006 page 95 of 180

REJ09B0019-0120

Table 13. 2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode

U0TB 0 to 7 Set transmission data

U0RB 0 to 7 Reception data can be read

OER Overrun error flag

U0BRG 0 to 7 Set a bit rate

U0MR SMD2 to SMD0 Set to “0012”

CKDIR Select the internal clock or external clock

U0C0 CLK1 to CLK0 Select the count source for the U0BRG register

TXEPT Transmit register empty flag

NCH Select TxD0 pin output mode

CKPOL Select the transfer clock polarity

UFORM Select the LSB first or MSB first

U0C1 TE Set this bit to “1” to enable transmission/reception

TI Transmit buffer empty flag

RE Set this bit to “1” to enable reception

RI Reception complete flag

UCON U0IRS Select the source of UART0 transmit interrupt

U0RRM Set this bit to “1” to use continuous receive mode

TXDISEL Set to “0”

TXDIEN Set to “0”

NOTES:

1. Not all register bits are described above. Set those bits to “0” when writing to the registers in clock

synchronous serial I/O mode.

Table 13.3 lists the functions of the I/O pins during clock synchronous serial I/O mode. Note that for a

period from when the UART0 operation mode is selected to when transfer starts, the TxD0 pin outputs an

“H”. (If the NCH bit is set to “1”(N-channel open-drain output), this pin is in high-impedance state.)

Table 13.3 Pin Functions

Pin name Function Method of selection

TxD

(P1

)

Serial data output

Serial data input

Transfer clock output

Transfer clock input

(Outputs dummy data when performing reception only)

RxD

(P1

)

CLK

(P1

)

U0MR register CKDIR bit=0

U0MR register CKDIR bit=1

PD1 register PD1_6 bit=0

PD1 register PD1_5 bit=0

(P1

can be used as an input port when performing transmission only)

1 2 ... 100 101 102 103 104 105 106 107 108 109 110 ... 198 199

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