Renesas R8C/Tiny Series Manuale Scaricare il pdf (Pagina 42)

R8C/10 Group 9. Bus

Rev.1.20 Jan 27, 2006 page 32 of 180

REJ09B0019-0120

9. Bus

During access, the ROM/RAM and the SFR have different bus cycles. Table 9.1 shows bus cycles for

access space.

The ROM/RAM and SFR are connected to the CPU through an 8-bit bus. When accessing in word (16

bits) units, these spaces are accessed twice in 8-bit units. Table 9.2 shows bus cycles in each access

space.

Space

Even address

byte access

CPU clock

Data

Address

SFR, Data flash

Program ROM/RAM

Even

Odd

Data

Odd

Odd Odd+1 Odd Odd+1

Even

Even+1

Data

Address

Data

Address

Data

Address

Data

Address

Data

Address

Data

Address

Data

Address

Odd address

byte access

Even address

word access

Odd address

word access

Data

Even

CPU clock

Table 9.1 Bus Cycles for Access Space

Access space Bus cycle

SFR/Data flash 2 CPU clock cycles

Program ROM/RAM 1 CPU clock cycles

Table 9.2 Access Unit and Bus Operation

1 2 ... 37 38 39 40 41 42 43 44 45 46 47 ... 198 199

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Renesas R8C/Tiny Series Manuale Pagina 42

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