Renesas PROM Programming Adapter PCA7408 Manuale Utente Pagina 52
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M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Rev.1.00 Oct 01, 2002 page 52 of 110
REJ03B0134-0100Z
Fig. 8.9.2 P3 output mode control register
Fig. 8.9.3 DA conversion register i (i = 1, 2)
b
7b
6b
5b4b
3b
2b
1b
0
D
A
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
i
(
i
=
1
,
2
)
(
D
A
i
)
[
A
d
d
r
e
s
s
e
s
0
0
D
E1
6,
0
0
D
F1
6]
A
f
t
e
r
r
e
s
e
t
D
A
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
i
0
to
5
6
0
0
D
A
c
o
n
v
e
r
s
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
(
D
A
i
0
t
o
D
A
i
5
)
b
0
b
1
b
2
b
3
b
4 b5
1
000000
00000
0
0000
0
0
111
1
1
11111
1
111111
:
1
/
6
4
V
c
c
:
2
/
6
4
V
c
c
:
6
1
/
6
4
V
c
c
:
6
2
/
6
4
V
c
c
:
6
3
/
6
4
V
c
c
: 0/64V
cc
0
7 0
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
T
h
e
s
e
b
i
t
s
a
r
e
w
r
i
t
e
d
i
s
a
b
l
e
b
i
t
s
.
W
h
e
n
t
h
e
s
e
b
i
t
s
a
r
e
r
e
a
d
o
u
t
,
t
h
e
v
a
l
u
e
s
a
r
e
“
0
.
”
R
—
R
W
R
W
R
W
BN
a
m
e
F
u
n
c
t
i
o
n
s
F
i
x
t
h
i
s
b
i
t
t
o
“
0
.
”
N
o
t
e
: W
h
e
n
u
s
e
M
3
7
2
2
1
M
4H/M6H/M8H/MAH-XXXSP/FP,
t
h
e
r
e
i
s
n
o
t
t
h
i
s
r
e
g
i
s
t
e
r
.
F
i
x
t
o
“
0
0
1
6.
”
b7 b
6b
5b
4b
3b
2b
1b
0
P
3
o
u
t
p
u
t
m
o
d
e
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
3
S
)
[
A
d
d
r
e
s
s
0
0
C
D
1
6]
P
3
o
u
t
p
u
t
m
o
d
e
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0
4 to 7
P
3
0
o
u
t
p
u
t
f
o
r
m
s
e
l
e
c
t
i
o
n
b
i
t
(
P
3
0
S
)
0:
CMOS
output
1: N-channel open-drain output
1
P
3
1
o
u
t
p
u
t
f
o
r
m
s
e
l
e
c
t
i
o
n
b
i
t
(
P
3
1
S
)
0:
CMOS
output
1: N-channel open-drain output
2
D
A
1
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
(
D
A
1
S
)
0:
P
3
0
i
nput/output
1: DA1 output
3
D
A
2
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
(
D
A
2
S
)
0:
P
3
1
i
nput/output
1: DA2 output
After reset
R
W
BN
a
m
e
F
u
n
c
t
i
o
n
s
0
0
0
0
0
R
W
R
W
R
W
R
W
R—
N
o
t
h
i
n
g
i
s
a
s
s
i
g
n
e
d
.
T
h
e
s
e
b
i
t
s
a
r
e
w
r
i
t
e
d
i
s
a
b
l
e
b
i
t
s
.
W
h
e
n
t
h
e
s
e
b
i
t
s
a
r
e
r
e
a
d
o
u
t
,
t
h
e
v
a
l
u
e
s
a
r
e
“
0
.
”
- 1. DESCRIPTION 0
- 2. FEATURES 0
- 3. APPLICATION 0
- REJ03B0134-0100Z 1
- Address 00E016 2
- Addresses 00DE16 and 00DF16 2
- Addresses 00E116 and 00E216 3
- Address 00E416 3
- Addresses 00E616 to 00E916 4
- Address 00E516 4
- Address 00EA16 5
- Addresses 00EC16 5
- Address 00ED16 6
- Addresses 00EE16 6
- Address 00EF16 7
- Addresses 00F416 7
- Address 00F516 8
- Addresses 00F916 8
- Address 00FB16 9
- Addresses 00FC16 9
- Address 00FD16 10
- Addresses 00FE16 10
- Address 00FF16 11
- Addresses 021B16 11
- 42P2R-A/E 13
- REVISION HISTORY 14
- RENESAS SALES OFFICES 15
- 8. FUNCTION BLOCK DESCRIPTION 16
- 8.1.1 CPU Mode Register 16
- RCR1 RCR0 21
- TABLE OF CONTENTS 24
- (4) Serial I/O interrupt 25
- (5) f(XIN)/4096 interrupt 25
- (6) Multi-master I 25
- C-BUS interface interrupt 25
- (7) BRK instruction interrupt 25
- 8.4 TIMERS 29
- 8.4.1 Timer 1 29
- 8.4.2 Timer 2 29
- 8.4.3 Timer 3 29
- 8.4.4 Timer 4 29
- Timer 34 Mode Register 30
- 8.5 SERIAL I/O 32
- 16), and the transfer 33
- OUT pin. Transfer 33
- 4. PIN CONFIGURATION 35
- Outline 42P4B 35
- Outline 42P2R-A/E 35
- 8.6 MULTI-MASTER I 37
- C-BUS INTERFACE 37
- C Data Shift Register 38
- C Address Register 39
- 16) is used to set ACK 40
- C Control Register 42
- (1) 7-bit addressing format 47
- (2) 10-bit addressing format 47
- (5) Writing to I 50
- C status register 50
- 8.8 A-D COMPARATOR 56
- 5. FUNCTIONAL BLOCK DIAGRAM 57
- 8.9 D-A CONVERTER 59
- 8.10 ROM CORRECTION FUNCTION 61
- 8.11 OSD FUNCTIONS 62
- OSD Control Register 65
- 8.11.1 Display Position 66
- 6. PERFORMANCE OVERVIEW 68
- Vertical Position Register i 69
- Horizontal Position Register 70
- 8.11.2 Character Size 71
- 8.11.3 Clock for OSD 73
- 8.11.4 Memory for OSD 74
- Border Selection Register 80
- 8.11.7 Multiline Display 81
- 8.11.8 OSD Output Pin Control 82
- 8.13. RESET CIRCUIT 85
- 8.14 CLOCK GENERATING CIRCUIT 86
- 8.17 ADDRESSING MODE 87
- 8.18 MACHINE INSTRUCTIONS 87
- 9. TECHNICAL NOTES 87
- 8.16 AUTO-CLEAR CIRCUIT 87
- 10. ABSOLUTE MAXIMUM RATINGS 88
- 7. PIN DESCRIPTION 90
- + Power source voltage 91
- 15. MULTI-MASTER I 92
- 16. PROM PROGRAMMING METHOD 93
- M37221EASP 95
- M37221EAFP 95
- 19. APPENDIX 96
- Pin Configuration (TOP VIEW) 96
- Memory Map 98
- Register (SFR) 100
- Program Counter at Reset 104
- Structure of Register 105
- Address 00C716 106
- Address 00CB16 107
- Address 00CD16 107
- Address 00D516 108
- Address 00D616 108
- Address 00D816 109
- Address 00D716 109
- Address 00D916 110
- Address 00DA16 110
- Address 00DB16 111
- Address 00DC16 111
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