Renesas PROM Programming Adapter PCA7408 Manuale Utente Pagina 13
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M37221M4H/M6H/M8H/MAH–XXXSP/FP M37221EASP/FP
Rev.1.00 Oct 01, 2002 page 13 of 110
REJ03B0134-0100Z
8.2 MEMORY
8.2.1 Special Function Register (SFR) Area
The special function register (SFR) area in the zero page includes
control registers such as I/O ports and timers.
8.2.2 RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
8.2.3 ROM
ROM is used for storing user programs as well as the interrupt vector
area.
8.2.4 OSD RAM
RAM used for specifying the character codes and colors for display.
8.2.5 OSD ROM
ROM used for storing character data for display.
8.2.6 Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
8.2.7 Zero Page
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area is pos-
sible with only 2 bytes in the zero page addressing mode.
8.2.8 Special Page
The special page addressing mode can be used to specify memory
addresses in the special page area. Access to this area is possible
with only 2 bytes in the special page addressing mode.
8.2.9 ROM Correction Memory (RAM)
This is used as the program area for ROM correction.
Fig. 8.2.1 Memory Map (M37221M4H/M6H-XXXSP/FP)
0
0
0
0
1
6
00C0
16
00FF
16
0
1
B
F
1
6
06B7
16
A
0
0
0
1
6
SFR area
Not used
Not used
N
o
t
u
s
e
d
F
F
F
F
1
6
F
F
D
E
1
6
FF00
16
0600
16
I
n
t
e
r
r
u
p
t
v
e
c
t
o
r
a
r
e
a
N
o
t
u
s
e
d
10000
16
11FFF
16
1FFFF
16
OSD ROM
(8K bytes)
S
p
e
c
i
a
l
p
a
g
e
OSD RAM
(96 bytes)
(See note)
Zero page
Note: Refer to Table 8.11.4 OSD RAM.
■
M
3
7
2
2
1
M
4
H/M6H
-
X
X
X
S
P
/
F
P
C000
16
0
1
7
F
1
6
M37221M6H-
XXXSP/FP
RAM
(448 bytes)
ROM
(16K bytes)
ROM
(24K bytes
)
M37221M6H-
XXXSP/FP
M37221M4H-
XXXSP/FP
02FF
16
0
2
C
0
16
02E0
16
ROM correction function
Vector 1: address 02C0
16
Vector 2: address 02E0
16
M37221M4H-
XXXSP/FP
RAM
(384 bytes)
- 1. DESCRIPTION 0
- 2. FEATURES 0
- 3. APPLICATION 0
- REJ03B0134-0100Z 1
- Address 00E016 2
- Addresses 00DE16 and 00DF16 2
- Addresses 00E116 and 00E216 3
- Address 00E416 3
- Addresses 00E616 to 00E916 4
- Address 00E516 4
- Address 00EA16 5
- Addresses 00EC16 5
- Address 00ED16 6
- Addresses 00EE16 6
- Address 00EF16 7
- Addresses 00F416 7
- Address 00F516 8
- Addresses 00F916 8
- Address 00FB16 9
- Addresses 00FC16 9
- Address 00FD16 10
- Addresses 00FE16 10
- Address 00FF16 11
- Addresses 021B16 11
- 42P2R-A/E 13
- REVISION HISTORY 14
- RENESAS SALES OFFICES 15
- 8. FUNCTION BLOCK DESCRIPTION 16
- 8.1.1 CPU Mode Register 16
- RCR1 RCR0 21
- TABLE OF CONTENTS 24
- (4) Serial I/O interrupt 25
- (5) f(XIN)/4096 interrupt 25
- (6) Multi-master I 25
- C-BUS interface interrupt 25
- (7) BRK instruction interrupt 25
- 8.4 TIMERS 29
- 8.4.1 Timer 1 29
- 8.4.2 Timer 2 29
- 8.4.3 Timer 3 29
- 8.4.4 Timer 4 29
- Timer 34 Mode Register 30
- 8.5 SERIAL I/O 32
- 16), and the transfer 33
- OUT pin. Transfer 33
- 4. PIN CONFIGURATION 35
- Outline 42P4B 35
- Outline 42P2R-A/E 35
- 8.6 MULTI-MASTER I 37
- C-BUS INTERFACE 37
- C Data Shift Register 38
- C Address Register 39
- 16) is used to set ACK 40
- C Control Register 42
- (1) 7-bit addressing format 47
- (2) 10-bit addressing format 47
- (5) Writing to I 50
- C status register 50
- 8.8 A-D COMPARATOR 56
- 5. FUNCTIONAL BLOCK DIAGRAM 57
- 8.9 D-A CONVERTER 59
- 8.10 ROM CORRECTION FUNCTION 61
- 8.11 OSD FUNCTIONS 62
- OSD Control Register 65
- 8.11.1 Display Position 66
- 6. PERFORMANCE OVERVIEW 68
- Vertical Position Register i 69
- Horizontal Position Register 70
- 8.11.2 Character Size 71
- 8.11.3 Clock for OSD 73
- 8.11.4 Memory for OSD 74
- Border Selection Register 80
- 8.11.7 Multiline Display 81
- 8.11.8 OSD Output Pin Control 82
- 8.13. RESET CIRCUIT 85
- 8.14 CLOCK GENERATING CIRCUIT 86
- 8.17 ADDRESSING MODE 87
- 8.18 MACHINE INSTRUCTIONS 87
- 9. TECHNICAL NOTES 87
- 8.16 AUTO-CLEAR CIRCUIT 87
- 10. ABSOLUTE MAXIMUM RATINGS 88
- 7. PIN DESCRIPTION 90
- + Power source voltage 91
- 15. MULTI-MASTER I 92
- 16. PROM PROGRAMMING METHOD 93
- M37221EASP 95
- M37221EAFP 95
- 19. APPENDIX 96
- Pin Configuration (TOP VIEW) 96
- Memory Map 98
- Register (SFR) 100
- Program Counter at Reset 104
- Structure of Register 105
- Address 00C716 106
- Address 00CB16 107
- Address 00CD16 107
- Address 00D516 108
- Address 00D616 108
- Address 00D816 109
- Address 00D716 109
- Address 00D916 110
- Address 00DA16 110
- Address 00DB16 111
- Address 00DC16 111
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