48
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C8 Group
Resolution
Absolute accuracy
(excluding quantization error)
Conversion time
Analog port input current
Unit
Bits
LSB
LSB
µs
µA
Limits
Parameter
Min.
30.5
Typ.
0.5
Max.
10
±4
±6
34
5.0
Symbol
VCC = 2.7–5.5 V
VCC = 2.5–2.7 V (Ta = –10 to 50 °C)
f(XIN) = 4 MHz (Note)
Test conditions
—
—
tconv
IIA
Table 17 A-D converter characteristics
(Vcc = 2.2 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, f(XIN) ≤ 4 MHz, in middle-speed/high-speed mode)
Note: When main clock is selected as system clock.
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RxD-SCLK)
th(SCLK-RxD)
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0, INT1 input “H” pulse width
INT0, INT1 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input setup time
Serial I/O input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RxD-SCLK)
th(SCLK-RxD)
Limits
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
2
125
45
40
250
105
105
80
80
800
370
370
220
100
Typ. Max.
Symbol Unit
Limits
µs
ns
ns
ns
ns
ns
ns
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
2
125
250
45
100
40
100
2/f(XIN)
tc(CNTR)/2–20
tc(CNTR)/2–20
230
230
2000
950
950
400
200
Typ. Max.
Symbol Unit
Table 18 Timing requirements 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Reset input “L” pulse width
Main clock input cycle time (XIN input) Vcc = 2.7 to 4.0 V
Main clock input cycle time (XIN input) Vcc = 2.2 to 2.7 V
Main clock input “H” pulse width Vcc = 2.7 to 4.0 V
Main clock input “H” pulse width Vcc = 2.2 to 2.7 V
Main clock input “L” pulse width Vcc = 2.7 to 4.0 V
Main clock input “L” pulse width Vcc = 2.2 to 2.7 V
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0, INT1 input “H” pulse width
INT0, INT1 input “L” pulse width
Serial I/O clock input cycle time (Note)
Serial I/O clock input “H” pulse width (Note)
Serial I/O clock input “L” pulse width (Note)
Serial I/O input setup time
Serial I/O input hold time
Table 19 Timing requirements 2 (mask ROM version) (Vcc = 2.2 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Note: When bit 6 of address 001A16 is “1”.
Divide this value by four when bit 6 of address 001A
16 is “0”.
Note: When bit 6 of address 001A
16 is “1”.
Divide this value by four when bit 6 of address 001A
16 is “0”.
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