Renesas PROM Programming Adapter PCA7447FP Informazioni Techniche Pagina 33
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30
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C8 Group
Fig. 28 Structure of LCD control register
Table 7 Maximum number of display pixels at each duty ratio
Duty ratio Maximum number of display pixel
16 ✕ 68 dots
(5 ✕ 7 dots + cursor 2 lines)
32 ✕ 52 dots
(5 ✕ 7 dots + cursor 4 lines)
16
32
LCD Controller/Driver Function
The controller/driver performs the bias control and the time sharing
control by the LCD control registers 1, 2 (LC1, LC2), and the LCD
mode register (LM). The data of corresponding LCDRAM is output
from the segment pins according to the output timing of the common
pins.
The 38C8 group has the voltage multiplier only for LCD in addition to
LCD controller/driver .
[LCD mode register (LM)] 003916
The LCD mode register is used for setting the LCD controller/driver
according to the LCD panel used.
[LCD control register 1 (LC1)] 003716
The LCD control register 1 controls the voltage multiplier and built-in
resistance.
[LCD control register 2 (LC2)] 003816
The LCD control register 2 is write-only. Setting “1” to bit 5 makes
built-in resistance low resistance, and can raise drivability of the seg-
ment pins and the common pins.
Note: When executing the STP instruction while operating LCD, ex-
ecute the STP instruction after prohibiting LCD (set “0” to bit 3
of the LCD mode regsiter).
LCD control register 1
(LC1: address 0037
16)
b7 b0
N
o
t
e
1
:
C
o
n
s
u
m
p
t
i
o
n
c
u
r
r
e
n
t
c
a
n
b
e
r
e
d
u
c
e
d
b
y
r
e
s
t
r
a
i
n
t
o
f
d
r
i
v
a
b
i
l
i
t
y
.
B
u
t
a
n
i
r
r
e
g
u
l
a
r
d
i
s
p
l
a
y
m
i
g
h
t
b
e
c
a
u
s
e
d
a
c
c
o
r
d
i
n
g
t
o
t
h
e
p
a
n
e
l
o
r
t
h
e
d
i
s
p
l
a
y
p
a
t
t
e
r
n
.
Not used (Do not write “1” to these bits.)
b7 b0
N
o
t
e
2
:
T
h
e
d
r
i
v
e
o
f
a
m
o
r
e
l
a
r
g
e
-
s
c
a
l
e
L
C
D
p
a
n
e
l
b
e
c
o
m
e
s
e
a
s
y
b
y
s
e
t
t
i
n
g
“
1
”
t
o
t
h
i
s
b
i
t
.
B
u
t
c
o
n
s
u
m
p
t
i
o
n
c
u
r
r
e
n
t
i
s
i
n
c
r
e
a
s
e
d
a
t
L
C
D
d
r
i
v
e
.
W
h
e
n
t
h
e
d
r
i
v
a
b
i
l
i
t
y
s
e
l
e
c
t
i
o
n
b
i
t
1
i
s
“
1
”
,
t
h
i
s
f
u
n
c
t
i
o
n
i
s
i
n
v
a
i
d
.
b7 b0
Note 3: LCDCK is a clock for a LCD timing controller.
Internal clock
φ
is X
CIN
divided by 2 in the low-speed mode.
✽ When selecting 32 duty, functions of pins 135 to 142 become COM16 to COM23,
and functions of pins 75 to 82 become COM24 to COM31.
N
o
t
u
s
e
d
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
e
s
e
b
i
t
s
.
)
Duty ratio selsection bit
✽
1
:
3
2
d
u
t
y
(
u
s
e
C
O
M
0–
C
O
M3
1)
0
:
1
6
d
u
t
y
(
u
s
e
C
O
M
0–
C
O
M1
5)
N
o
t
u
s
e
d
(
D
o
n
o
t
w
r
i
t
e
“
0
”
t
o
t
h
i
s
b
i
t
.
)
L
C
D
d
i
s
p
l
a
y
R
A
M
a
d
d
r
e
s
s
s
e
l
e
c
t
i
o
n
b
i
t
0
:
3
p
a
g
e
1
:
0
p
a
g
e
L
C
D
e
n
a
b
l
e
b
i
t
0
:
L
C
D
O
F
F
1
:
L
C
D
O
N
L
C
D
d
r
i
v
e
t
i
m
i
n
g
s
e
l
e
c
t
i
o
n
b
i
t
0
:
A
t
y
p
e
1
:
B
t
y
p
e
L
C
D
C
K
d
i
v
i
s
i
o
n
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
s
b
6
b
5
0
0
:
C
l
o
c
k
i
n
p
u
t
0
1
:
2
d
i
v
i
s
i
o
n
o
f
c
l
o
c
k
i
n
p
u
t
1
0
:
4
d
i
v
i
s
i
o
n
o
f
c
l
o
c
k
i
n
p
u
t
1
1
:
8
d
i
v
i
s
i
o
n
o
f
c
l
o
c
k
i
n
p
u
t
L
C
D
C
K
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
N
o
t
e
3
)
0
:
f
(
X
I
N)
/
1
0
2
4
1
:
f
(
X
C
I
N)
/
1
6
LCD mode register
(LM: address 0039
16)
V
o
l
t
a
g
e
m
u
l
t
i
p
l
i
e
r
e
n
a
b
l
e
b
i
t
0
:
V
o
l
t
a
g
e
m
u
l
t
i
p
l
i
e
r
s
t
o
p
1
:
V
o
l
t
a
g
e
m
u
l
t
i
p
l
i
e
r
o
p
e
r
a
t
i
n
g
N
o
t
u
s
e
d
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
i
s
b
i
t
.
)
Drivability selection bit 1
0 : Normal (Drivability selection
bit 2 valid)
1 : Restraint
(
N
o
t
e
1
)
LCD control register 2
(LC2: address 0038
16)
N
o
t
u
s
e
d
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
e
s
e
b
i
t
s
.
)
D
r
i
v
a
b
i
l
i
t
y
s
e
l
e
c
t
i
o
n
b
i
t
2
0
:
N
o
r
m
a
l
1
:
R
e
i
n
f
o
r
c
i
n
g
(
N
o
t
e
2
)
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