Renesas Single-Chip Microcomputer M34519T-MCU Specifiche Scaricare il pdf (Pagina 15)

The increased amount of address calculations in the CPU in the case of complex addressing causes disturbances in the pipeline. As

a result, address calculation becomes a bottleneck for pipeline processing making it difcult to raise the frequency and increase the

performance. The V850 microcontrollers avoid this problem by supporting only simple addressing.

Simple addressing

The V850 microcontrollers employ a 2-byte instruction code to perform basic processing to enable compact program development

equivalent to 16-bit CISC microcontrollers.

1.03

1.02

1.48

1.00

Object Code Size Comparison

(Dhrystone 1.1/Large model)

16-bitV (CISC)

78K4 (CISC)

V850 (RISC)

/MIPS

32 (RISC)

• Improved object efciency through ROMization programming

Application of 2-byte instructions to all basic processing, consisting of load, store,

arithmetic/logic operations, and branching.

• To realize ease of use, restrictions on 16-bit xed-length instructions are

partially removed through the incorporation of 32-bit instructions.

• Bit manipulation instructions, etc., are available.

2-byte basic instruction set

•

Operand addresses

reg1

031

disp16

016 1531

Signed extension

Memory subject to

manipulation

reg1

031

disp16

16 15

Signed extension

Memory subject to

manipulation

• Register addressing

Addressing that accesses the general-purpose register specied by the general-

purpose specication eld or a system register as an operand.

• Immediate addressing

Addressing of 5-bit data or 16-bit data for manipulation in the instruction code.

• Based addressing

Addressing that

accesses memory, with

the sum of the contents

of the general-purpose

16-bit displacement

(disp16) used as the

operand address.

• Bit addressing

Addressing that

accesses 1 bit of 1 byte

of the memory space,

with the sum of the

contents of the general-

purpose register (reg1)

and 16-bit displacement

(disp16) that has been

sign extended to word

length used as the

operand address.

•

Instruction addresses

26 2531

022 2131

Signed extension

disp22

026 2531

Memory subject to

manipulation

reg1

026 2531

Memory subject to

manipulation

• Register addressing (register indirect)

Transfer the contents of the general-purpose register specied by the instruction (reg1) to

the program counter (PC).

• Relative addressing (PC dependent)

Add 9 signed bits or 22 signed bits of data of the instruction code to the program counter.

Addressing modes

Processing time Processing time

All processing is standardized and efcient

Pipeline processing sequence

Pipeline Processing Time and CPU Operating Frequency

Operating

frequency held back

by slow processing

In case of excessive addressing

In case of simple addressing

Address calculation

Execution

Memory access

Writeback

Instruction fetch

The V850 microcontrollers support bit manipulation instructions ideal for manipulating the ags in I/O registers, which play a large

role in embedding control.

Object size

Execution time

Coding example

Item

4 bytes

4 clock cycles 4 clock cycles 8 clock cycles

When Used When Not Used

set1 6, ASIM00[r0] ld.b ASIM00[r0], r20

ori 0x0040, r20, r20

st.b r20, ASIM00[r0]

Save r20

Restore r20

add -4, sp

st.w r20, 0[sp]

ld.b ASIM00[r0], r20

ori 0x0040, r20, r20

st.b r20, ASIM00[r0]

ld.w 0[sp], r20

add 4, sp

12 bytes 24 bytes

Bit Manipulation

Instruction

• Improvement of operability of memory mapped

I/O devices for control applications

• Manipulation of any 1 bit of byte data in the

memory space

• Provision of test (tst1)/set (set1)/clear (clr1)/

invert (not1) instructions

• Effective for reducing object size and execution

time since ags can be manipulated in 1-bit

units using 1 instruction

Example: Setting bit 6 of ASIM00 register to 1

CISC-like instructions for embedding (bit manipulation instructions)

In the V850 microcontrollers, calculation results are reected in registers as status ags. As a result, the delay branching that can

occur in the RISC microcontrollers of other manufacturers does not occur and programs can be coded with the same feel as CISC

microcontrollers.

CISC Microcontroller V850

Other Manufacturers’ RISC Microcontroller

cmp/eq #0, r10

bt ZERO

cmp/pl r10

bt PLUS

bra MINUS

nop ;

For delay branching

cmp 0, r10

bz ZERO

/jointfilesconvert/436525/bgt PLUS

br MINUS

cmp ax, 0

jz ZERO

jgt PLUS

jmp MINUS

• Easy coding using an assembler

• Improved object efciency and execution speed

Multi-status ﬂags

The V850 microcontrollers can realize bit manipulations frequently used during signed data and image data processing using 1

instruction per clock cycle.

• Shifting of any number of bits (0 to 31) executable in 1 instruction per clock

cycle

Improved execution speed and object efciency

Effective for extracting arbitrary bit lengths of image data and signed data

(extracting code during MH/MR/MMR encoding, etc.)

Number of instructions4 1

V850

Number of execution clock cycles

4 1

Example: 27-bit logical right shift

SHR 27, Rn

Other manufacturers'

RISC microcontroller

SHR16 Rn

SHR8 Rn

SHR2 Rn

SHR Rn

Processing sequence

32-bit barrel shifter

The V850 microcontrollers provide a DSP function for executing high-speed multiplication and product-sum operations

indispensable for digital signal processing such as image and speech processing.

• Direct data handling via general-purpose registers

• Realization of digital signal processing through general-

purpose CPU

• High-speed 16-bit (V850, V850ES CPU) and 32-bit (V850E1

CPU) multiply/sum-of-products operations

(Multiply: 1 to 2 clocks, sum-of-products: 3 clocks)

• Effective for lter operations and matrix operations for

feedback calculations in speed, position, and other servo

control.

V850

General-purpose register

CPU

DSP

Memory

MUL

INT

CPU

ALU

CPU + DSP

MUL

SAT

ag

ALU

DSP function

ZERO: Zero processing

PLUS: Positive processing

MINUS: Negative processing

Example: Program that branches to positive/negative/zero according to register contents

28 29

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 50 51

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