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Harvard architecture

The V850 microcontrollers use Harvard architecture, which is designed so that the instruction bus and data bus can operate

independently from each other, thereby preventing pipeline operation problems and ensuring efcient instruction execution.

In the case of an architecture other than Harvard architecture, the MEM stage of

instruction 1 and the IF stage of instruction 4, and the MEM stage of instruction 2 and

the IF stage of instruction 5 conict, causing bus waits. This in turn causes the pipeline

operation to become disordered and lowers the instruction execution speed.

IF ID EX MEM

Instruction 1

Instruction 2

Instruction 3

Instruction 4

Instruction 5

---: Idles inserted due to bus wait

WBMEM

MEM

---

MEM

---

MEM

---

IDIF

IF ID EX

Pipeline Operation of Non-Harvard Architecture

CPU

Instruction bus

Data bus

Instruction

fetch

External

memory

On-chip

peripheral

I/O

Operand

data access

Internal

RAM

Internal

ROM

BCU

5-stage pipeline processing

The V850 microcontrollers use a 5-stage pipeline structure (5 stages from instruction fetch to writeback) that supports simultaneous

processing of 5 instructions, thus enabling the execution of almost all instructions in just one clock cycle.

ID EX WB

ID EX

MEM

MEM WB

ID EX MEM WB

IF ID EX MEM WB

Instruction 1

Instruction 2

Instruction 3

Instruction 4

Instruction 5

Instruction 6

IF: Instruction fetch

ID: Instruction decode

EX: Instruction execution

MEM: Memory access to target address

WB: Write execution result to register

Instruction 1

completion

Instruction 2

completion

Instruction 3

completion

An instruction is executed in each clock cycle

Instruction 4

completion

Instruction 5

completion

Instruction 6

completion

Internal system clock

V850 Architecture

The V850 microcontrollers are single-chip RISC microcontrollers that use an architecture optimized for embedding, and have the

following features:

5-stage pipeline processing

Harvard architecture

32 general-purpose registers

Simple addressing

2-byte basic instruction set

32-bit barrel shifter

Support of CISC-like instructions

Multi-status ﬂags DSP

General-purpose register conﬁguration System register conﬁguration

The number of registers can be selected from 22, 26, or 32 as a compiler option to efciently execute application programs. Unused

registers can be used as a software register bank for which backup and restore processing is not required during interrupt servicing

or task switching, which increases the processing speed.

Software register bank

interrupt

Program

execution

Program

execution

Interrupt servicing

instruction execution

Actual interrupt

servicing time

Normal

interrupt

Program

execution

Interrupt servicing

instruction execution

Program

execution

Actual interrupt

servicing time

User interrupt servicing routine execution time

Total interrupt servicing time

32 general-purpose registers

The V850 microcontrollers have 32 general-purpose registers. Along with a hardware environment that is ideal for program

execution, the development environment, including compilers, exploits these 32 registers to achieve program generation with

superior code efciency and execution performance.

1000

2000

3000

4000

Comparison of Performance/Object Efciency According to Number of Registers

Byte count (bytes)

Execution time (s)

Number of registersUsed C program: Servo control module

16 18 20 22 24 26 28 30 32

Byte count Execution time

For example, looking at the program execution time and

code size changes when the number of registers used by

the compiler is changed using the servo control module,

we can see that the larger the number of registers, the

better the program execution speed and the smaller

the code size. However, from about 26 registers, the

improvement in terms of execution speed and code size

becomes smaller, and in the neighborhood of 32 registers,

there are no more changes. This is why the V850

microcontrollers have been provided with 32 registers as

a strict minimum requirement.

Save the program counter, etc., to a backup

Execute the interrupt restore instruction.

Restore the program counter value, etc.,

from the backup register.

Save general-purpose registers to the stack.

Restore general-purpose registers from the

stack.

Address/data variable register

(If real-time OS being used does not use r2)

Zero Register

r10

r11

r12

r13

r14

r15

r16

r17

r18

r19

r21

r22

r23

r24

r25

r26

r27

r28

r29

r30

r31

r20

Name

r6-r29

r30

r31

Application Operation

Zero register

Assembler

reservation

Always holds "0"

Stack pointer

Global pointer

Text pointer

Element pointer

Link pointer

Program counter

Used as working register for

address generation

Used for stack frame

generation during function call

Used when accessing global

variables in the data area

Used as register

for specifying

the beginning of the text area

(program code allocation)

Address/data variable register

Used as base pointer

for address

generation during memory

access

Used during function

call by compiler

Holds instruction addresses

during program execution

Reserved for Address Generation

Stack Pointer (SP)

Global Pointer (GP)

Text Pointer (TP)

Link Pointer (LP)

Element Pointer (EP)

Program Counter

No.

6-15, 21-31

EIPC

EIPSW

FEPC

FEPSW

ECR

PSW

CTPC

CTPSW

DBPC

DBPSW

CTBP

Reserved

Application

Supported by

other than

V850 CPU

products

during interrupt

during NMI

Interrupt source register

Program status word

during CALLT execution

during exception/debug trap

CALLT base pointer

LDSR

STSR

×: Access prohibited

: Access enabled

LDSR: Instruction to load general-purpose register

contents to system register

STSR: Instruction to store system register contents to

general-purpose register

Operand

Specication

System

26 27

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 50 51

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