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Renesas PROM Programming Adapters PCA7438F-64A Specifiche Pagina 54

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Vedere la pagina 53
Rev.2.40 Jun 14, 2004 page 54 of 56
38C1 Group
twH(SCLK)
twL(SCLK)
td(SCLK-SOUT)
tV(SCLK-SOUT)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
twH(SCLK)
twL(SCLK)
td(SCLK-SOUT)
tV(SCLK-SOUT)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Limits
Parameter
Min.
tc(SCLK)/2–30
tc(SCLK)/2–30
–30
Typ.
25
25
Max.
140
30
30
200
40
40
Symbol Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P55/SOUT P-channel output disable bit of the serial I/O control register (bit 4 of address 001D16) is “0.”
2: The X
OUT, XCOUT pins are excluded.
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time P20–P27
CMOS output rising time P30–P34, P44–P47,
P50–P57, P60–P64 (Note 2)
CMOS output falling time (Note 2)
Table 21 Switching characteristics 1
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
tC(SCLK)/2–80
tC(SCLK)/2–80
–30
Typ.
60
60
Max.
350
80
80
400
120
120
Symbol Unit
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O output delay time (Note 1)
Serial I/O output valid time (Note 1)
Serial I/O clock output rising time
Serial I/O clock output falling time
CMOS output rising time P20–P27
CMOS output rising time P30–P34, P44–P47,
P50–P57, P60–P64 (Note 2)
CMOS output falling time (Note 2)
Table 22 Switching characteristics 2
(Vcc = 1.8 to 4.0 V (2.2 to 4.0 V for One Time PROM version), Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Notes 1: When the P55/SOUT P-channel output disable bit of the serial I/O control register (bit 4 of address 001D16) is “0.”
2: The X
OUT, XCOUT pins are excluded.
Fig. 50 Circuit for measuring output switching characteristics
M
easurement output p
i
n
1
0
0
p
F
C
M
O
S
o
u
t
p
u
t
N
ote:
Wh
en
bi
t 4 o
f
t
h
e ser
i
a
l
I/O
contro
l
reg
i
ster
(
a
dd
ress
001D
16
) is “1” (N-channel open-drain output mode).
N
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
(
N
o
t
e
)
1
k
Ω
1
0
0
p
F
M
easurement output p
i
n
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