Renesas PROM Programming Adapters PCA7438F-64A Specifiche

DESCRIPTIONThe 38C1 group is the 8-bit microcomputer based on the 740 fam-ily core technology.The 38C1 group has the LCD drive control circuit, an 8-c

Rev.2.40 Jun 14, 2004 page 10 of 5638C1 Group[CPU Mode Register (CPUM)] 003B16The CPU mode register contains the stack page selection bit andthe

Rev.2.40 Jun 14, 2004 page 11 of 5638C1 GroupMEMORYSpecial Function Register (SFR) AreaThe Special Function Register area in the zero page conta

Rev.2.40 Jun 14, 2004 page 12 of 5638C1 GroupFig. 10 Memory map of special function register (SFR)0 0 0 01 60 0 2 01 60 0 0 11 60 0 2 11 60 0 0

Rev.2.40 Jun 14, 2004 page 13 of 5638C1 GroupI/O PORTSDirection Registers (Ports P2–P6)The I/O ports (P2–P6) have direction registers which dete

Rev.2.40 Jun 14, 2004 page 14 of 5638C1 GroupFig. No.Related SFRsInput/OutputNamePinNon-Port FunctionI/O FormatTable 5 List of I/O port function

Rev.2.40 Jun 14, 2004 page 15 of 5638C1 GroupFig. 12 Port block diagram (1)( 2 ) P o r t P 2Segment output enable bitP u l l - d o w n c o

Rev.2.40 Jun 14, 2004 page 16 of 5638C1 GroupFig. 13 Port block diagram (2)S e r i a l I / O t r a n s m i t e n d s i g n a lS y n c h

Rev.2.40 Jun 14, 2004 page 17 of 5638C1 GroupFig. 14 Port block diagram (3)(13)Port P62P o r t l a t c hD a t a b u sTO U T o u t p u t

Rev.2.40 Jun 14, 2004 page 18 of 5638C1 GroupINTERRUPTSInterrupts occur by thirteen sources: five external, seven internal,and one software.Inte

Rev.2.40 Jun 14, 2004 page 19 of 5638C1 GroupFig. 15 Interrupt controlFig. 16 Structure of interrupt-related registersI n t e r r u p t r e

Rev.2.40 Jun 14, 2004 page 2 of 5638C1 GroupFig. 1 Pin configuration of M38C1XMX-XXXFP/HPPIN CONFIGURATION (TOP VIEW)O u t l i n e 6 4 P 6 U

Rev.2.40 Jun 14, 2004 page 20 of 5638C1 GroupKey Input Interrupt (Key-on Wake Up)A Key-on wake up interrupt request is generated by applying “L”

Rev.2.40 Jun 14, 2004 page 21 of 5638C1 GroupTIMERSThe 38C1 group has five timers: timer X, timer Y, timer 1, timer 2,and timer 3. Timer X and t

Rev.2.40 Jun 14, 2004 page 22 of 5638C1 GroupTimer XTimer X is a 16-bit timer that can be selected in one of four modesand can be controlled the

Rev.2.40 Jun 14, 2004 page 23 of 5638C1 GroupTimer YTimer Y is a 16-bit timer that can be selected in one of four modes.(1) Timer modeThe timer

Rev.2.40 Jun 14, 2004 page 24 of 5638C1 GroupTimer 1, Timer 2, Timer 3Timer 1, timer 2, and timer 3 are 8-bit timers. The count source foreach t

Rev.2.40 Jun 14, 2004 page 25 of 5638C1 GroupSerial I/OThe serial I/O function can be used only for clock synchronous se-rial I/O.For clock sync

Rev.2.40 Jun 14, 2004 page 26 of 5638C1 GroupFig. 24 Timing of serial I/O functionD7D0D1D2D3D4D5D6T r a n s f e r c l o c k ( N o t e 1 )S

Rev.2.40 Jun 14, 2004 page 27 of 5638C1 GroupA/D CONVERTERThe functional blocks of the A/D converter are described below.● A/D ConverterThe conv

Rev.2.40 Jun 14, 2004 page 28 of 5638C1 GroupFig. 27 Structure of ADKEY pin selection bitsb 7b 0P 4 d a t a r e g i s t e r ( A d d r e s

Rev.2.40 Jun 14, 2004 page 29 of 5638C1 GroupDefinition of A/D converter accuracyThe A/D conversion accuracy is defined below (refer to Figure 2

Rev.2.40 Jun 14, 2004 page 3 of 5638C1 GroupFUNCTIONAL BLOCK DIAGRAMFig. 2 Functional block diagramI / O p o r t P 4P 5 ( 8 )I / O p o r

Rev.2.40 Jun 14, 2004 page 30 of 5638C1 GroupLCD DRIVE CONTROL CIRCUITThe 38C1 group has the built-in Liquid Crystal Display (LCD) drivecontrol

Rev.2.40 Jun 14, 2004 page 31 of 5638C1 GroupFig. 30 Block diagram of LCD controller/driverf ( XC I N) / 3 2C O M0C O M1C O M2C O M3VS SVL 1VL

Rev.2.40 Jun 14, 2004 page 32 of 5638C1 GroupFig. 31 Example of circuit at each biasTable 8. Bias control and applied voltage to VL1–VL3Bias va

Rev.2.40 Jun 14, 2004 page 33 of 5638C1 Group (frequency of count source for LCDCK) (divider division ra

Rev.2.40 Jun 14, 2004 page 34 of 5638C1 GroupFig. 33 LCD drive waveform (1/2 bias, 1/1 bias)VL3VL2=VL1VSSVL3VSSC O M0C O M1C O M2C O M3SEG0C O

Rev.2.40 Jun 14, 2004 page 35 of 5638C1 GroupFig. 34 LCD drive waveform (1/3 bias)VL3VS SC O M0C O M1C O M2C O M3S E G0COM3C O M2 COM1 COM0C O

Rev.2.40 Jun 14, 2004 page 36 of 5638C1 GroupFig. 35 Structure of clock output control registerOTHER FUNCTION REGISTERS● φ clock output functio

Rev.2.40 Jun 14, 2004 page 37 of 5638C1 GroupFig. 37 Example of reset circuitRESET CIRCUITTo reset the microcomputer, RESET pin should be held

Rev.2.40 Jun 14, 2004 page 38 of 5638C1 GroupFig. 39 Internal state of microcomputer immediately after resetNote: The contents of all other reg

Rev.2.40 Jun 14, 2004 page 39 of 5638C1 GroupCLOCK GENERATING CIRCUITThe oscillation circuit of 38C1 group can be formed by connectingan oscilla

Rev.2.40 Jun 14, 2004 page 4 of 5638C1 GroupPIN DESCRIPTIONTable 1 Pin descriptionFunctionPinNameFunction except a port function• Apply voltage

Rev.2.40 Jun 14, 2004 page 40 of 5638C1 GroupFig. 42 Clock generating circuit block diagramSRQXI N- XO U T o s c i l l a t i o n s t o p b

Rev.2.40 Jun 14, 2004 page 41 of 5638C1 GroupFig. 43 State transitions of system clockR e s e t r e l e a s eXIN stopXCIN stopφ=f(ROSC)/8CM7=

Rev.2.40 Jun 14, 2004 page 42 of 5638C1 GroupNOTES ON PROGRAMMINGProcessor Status RegisterThe contents of the processor status register (PS) aft

Rev.2.40 Jun 14, 2004 page 43 of 5638C1 GroupNOTES ON USEVL3 pinWhen LCD drive control circuit is not used, connect VL3 to VCC.Countermeasures a

Rev.2.40 Jun 14, 2004 page 44 of 5638C1 Group(3) Oscillator concernsIn order to obtain the stabilized operation clock on the user systemand its

Rev.2.40 Jun 14, 2004 page 45 of 5638C1 GroupROM PROGRAMMING METHODThe built-in PROM of the blank One Time PROM version(M38C13E6FP/HP) can be re

Rev.2.40 Jun 14, 2004 page 46 of 5638C1 GroupELECTRICAL CHARACTERISTICSAbsolute Maximum RatingsTable 11 Absolute maximum ratingsParameterPower s

Rev.2.40 Jun 14, 2004 page 47 of 5638C1 GroupRecommended Operating ConditionsTable 12 Recommended operating conditions(Vcc = 1.8 to 5.5 V (One

Rev.2.40 Jun 14, 2004 page 48 of 5638C1 Group“H” total peak output current (Note 1)P20–P27, P30–P34“H” total peak output current (Note 1)P44–P47

Rev.2.40 Jun 14, 2004 page 49 of 5638C1 GroupTable 14 Recommended operating conditions (Vcc = 1.8 to 5.5 V (One Time PROM version: 2.2 to 5.5 V

Rev.2.40 Jun 14, 2004 page 5 of 5638C1 GroupPART NUMBERINGFig. 3 Part numberingM 3 8 C 1 3M6-X X XF PP r o d u c tR O M / P R O M s i

Rev.2.40 Jun 14, 2004 page 50 of 5638C1 GroupIOH = –1.0 mAIOH = –0.2 mAVCC = 1.8 to 5.5 V (Note)IOH = –2.5 mAIOH = –0.5 mAVCC = 1.8 to 5.5 V (No

Rev.2.40 Jun 14, 2004 page 51 of 5638C1 GroupPowersourcecurrentLimitsParameterMin. Typ.3.00.81.54.70.92.50.60.30.40.90.30.61.20.80.81.80.91.00.5

Rev.2.40 Jun 14, 2004 page 52 of 5638C1 GroupA/D Converter CharacteristicsTable 17 A/D converter recommended operating condition(Vcc = 2.0 to 5

Rev.2.40 Jun 14, 2004 page 53 of 5638C1 GroupReset input “L” pulse widthMain clock input cycle time (XIN input)Main clock input “H” pulse widthM

Rev.2.40 Jun 14, 2004 page 54 of 5638C1 GrouptwH(SCLK)twL(SCLK)td(SCLK-SOUT)tV(SCLK-SOUT)tr(SCLK)tf(SCLK)tr(CMOS)tf(CMOS)twH(SCLK)twL(SCLK)td(SC

Rev.2.40 Jun 14, 2004 page 55 of 5638C1 GroupFig. 51 Timing chart0 . 2 VC Ctd( SC L K- SO U T)tf0.2VCC0 . 8 VC C0.8VCCtrts u( SI N- SC L K)th( S

Rev.2.40 Jun 14, 2004 page 56 of 5638C1 GroupPACKAGE OUTLINELQFP64-P-1010-0.50 –Weight(g)–JEDEC CodeEIAJ Package CodeLead MaterialCu Alloy64P6Q-

REVISION HISTORY 38C1 GROUP DATA SHEETRev. Date DescriptionPage Summary(1/2)1.0 01/16/022.0 03/28/022.1 05/09/02First Edition1 FEATURES; • Interrupts

REVISION HISTORY 38C1 GROUP DATA SHEETRev. Date DescriptionPage Summary(2/2)2.2Nov. 07, 20032.30Dec. 24, 20032..40 Jun. 14, 200425 Notes on Serial I

Keep safety first in your circuit designs!1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more relia

Rev.2.40 Jun 14, 2004 page 6 of 5638C1 GroupGROUP EXPANSIONRenesas plans to expand the 38C1 group as follows.Memory TypeSupport for Mask ROM ver

Rev.2.40 Jun 14, 2004 page 7 of 5638C1 GroupFUNCTIONAL DESCRIPTIONCENTRAL PROCESSING UNIT (CPU)The 38C1 group uses the standard 740 family instr

Rev.2.40 Jun 14, 2004 page 8 of 5638C1 GroupTable 3 Push and pop instructions of accumulator or processor status registerAccumulatorProcessor s

Rev.2.40 Jun 14, 2004 page 9 of 5638C1 Group[Processor status register (PS)]The processor status register is an 8-bit register consisting of 5fl