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Renesas PCA7429G02 Informazioni Techniche Pagina 39

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36
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37272M6/M8–XXXSP/FP, M37272MA–XXXSP
M37272E8SP/FP, M37272EFSP
MITSUBISHI MICROCOMPUTERS
Rev. 1.3
(8) Bit 7: Communication mode specification bit
(master/slave specification bit: MST)
This bit is used for master/slave specification for data communica-
tion. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are received,
and data communication is performed in synchronization with the
clock generated by the master. When this bit is “1,” the master is
specified and a START condition and a STOP condition are gener-
ated, and also the clocks required for data communication are gen-
erated on the SCL.
The MST bit is cleared to “0” in one of the following conditions.
• Immediately after completion of 1-byte data transmission when
arbitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START
condition duplication preventing function (Note).
• At reset
Fig. 8.6.7 I
2
C Status Register
b
7b
6b
5b
4b
3b
2b
1b
0
I
2
C
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
S
1
)
[
A
d
d
r
e
s
s
0
0
F
8
1
6
]
I
2
C
S
t
a
t
u
s
R
e
g
i
s
t
e
r
0
3
4
5
6
,
7
b
7
b
6
0
0
:
S
l
a
v
e
r
e
c
i
e
v
e
m
o
d
e
0
1
:
S
l
a
v
e
t
r
a
n
s
m
i
t
m
o
d
e
1
0
:
M
a
s
t
e
r
r
e
c
i
e
v
e
m
o
d
e
1
1
:
M
a
s
t
e
r
t
r
a
n
s
m
i
t
m
o
d
e
1
2
0
0
0
1
0
B
N
a
m
e
F
u
n
c
t
i
o
n
s
A
f
t
e
r
r
e
s
e
t
R
W
C
o
m
m
u
n
i
c
a
t
i
o
n
m
o
d
e
s
p
e
c
i
f
i
c
a
t
i
o
n
b
i
t
s
(
T
R
X
,
M
S
T
)
0
:
B
u
s
f
r
e
e
1
:
B
u
s
b
u
s
y
B
u
s
b
u
s
y
f
l
a
g
(
B
B
)
0
:
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
1
:
N
o
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
i
s
s
u
e
d
I
2
C
-
B
U
S
i
n
t
e
r
f
a
c
e
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
(
P
I
N
)
0
:
N
o
t
d
e
t
e
c
t
e
d
1
:
D
e
t
e
c
t
e
d
A
r
b
i
t
r
a
t
i
o
n
l
o
s
t
d
e
t
e
c
t
i
n
g
f
l
a
g
(
A
L
)
(
S
e
e
n
o
t
e
)
0
:
A
d
d
r
e
s
s
m
i
s
m
a
t
c
h
1
:
A
d
d
r
e
s
s
m
a
t
c
h
S
l
a
v
e
a
d
d
r
e
s
s
c
o
m
p
a
r
i
s
o
n
f
l
a
g
(
A
A
S
)
(
S
e
e
n
o
t
e
)
0
:
N
o
g
e
n
e
r
a
l
c
a
l
l
d
e
t
e
c
t
e
d
1
:
G
e
n
e
r
a
l
c
a
l
l
d
e
t
e
c
t
e
d
G
e
n
e
r
a
l
c
a
l
l
d
e
t
e
c
t
i
n
g
f
l
a
g
(
A
D
0
)
(
S
e
e
n
o
t
e
)
0
:
L
a
s
t
b
i
t
=
“
0
”
1
:
L
a
s
t
b
i
t
=
“
1
”
L
a
s
t
r
e
c
e
i
v
e
b
i
t
(
L
R
B
)
(
S
e
e
n
o
t
e
)
N
o
t
e
:
T
h
e
s
e
b
i
t
s
a
n
d
f
l
a
g
s
c
a
n
b
e
r
e
a
d
o
u
t
,
b
u
t
c
a
n
n
n
o
t
b
e
w
r
i
t
t
e
n
.
I
n
d
e
t
e
r
m
i
n
a
t
e
R—
R—
R—
R—
RW
R
W
0
R
W
(
S
e
e
n
o
t
e
)
(
S
e
e
n
o
t
e
)
(
S
e
e
n
o
t
e
)
(
S
e
e
n
o
t
e
)
Fig. 8.6.8 Interrupt Request Signal Generation Timing
S
C
L
P
I
N
I
I
C
I
R
Q
Note:The START condition duplication prevention function disables the START
condition generation, reset of bit counter reset, and SCL output, when
the following condition is satisfied:
a START condition is set by another master device.
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