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V850E2/MN4 Timer Array Unit Control

R01AN0922EJ0100 Rev.1.00 Page 41 of 54

Jan 13, 2012

• TAUJn channel mode OS register (TAUJnCMORm)

This register controls channel m operation.

In this sample program, channel 0 in the TAUJ0 is set to capture & one count mode and disables the start trigger during

operation by using the valid edge of the TAUJ0TTIN0 input signal as an external start trigger and the reverse edge as a

stop trigger.

Figure 4.36 TAUJnCMORm Register Format (1/3)

1 2 ... 36 37 38 39 40 41 42 43 44 45 46 ... 56 57

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