Renesas User System Interface Cable HS36049ECH61H Manuale Utente Pagina 9

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H8 MCUs: Faster
Execution Times
Besides maintaining compat-
ibility within the family,
H8 CPUs have been optimized
for high performance.
The majority of the instruc-
tions in the powerful CISC
instruction set will execute
in one clock cycle, giving
RISC-like operation.
Enhanced Hardware
for Performance
Enhanced multipliers and
dividers are included in the
CPU core to boost throughput
for mathematical operations
and further enhance the
performance of the CPU cores.
The H8S/2600 and H8SX
CPU cores each have a
hardware MAC (Multiply and
Accumulate) block for extra
performance in applications
that involve data computa-
tions.
H8 MCU System
Performance
H8 microcontrollers are designed to
deliver high throughput for excellent
application performance.
For example, their CISC CPU cores
execute most instructions in just one
clock cycle, and their Advanced
Data Management peripherals
utilize a 3-bus architecture to speed
data transfers.
Also, the on-chip Flash can be
accessed in a single cycle, achieving
the best possible performance
per MHz.
H8/300 H8/300H H8S/2000 H8S/2600 H8SX
Basic Instructions Execution 2 cycles 2 cycles 1 cycle 1 cycle 1 cycle
Bus Width 8-bit 16-bit 16-bit 16-bit 32-bit
No. of Instructions 57 64 65 69 87
Address Space 64KB 16MB 16MB 16MB 4GB
9 MIPS
H8S/2000
@ 20 MHz
11 MIPS
H8S/2000
@ 25 MHz
15.2 MIPS
H8S/2600
@ 33 MHz
H8SX
@ 35 MHz
35 MIPS
H8SX
@ 50 MHz
50 MIPS
Dhrystone 1.1 MIPS value
40
30
20
10
50
Instruction H8S H8SX
MULXU.B 3 1
MULXU.W 4 1
MULXS.B 4 2
MULXS.W 5 2
MULU.W - 2
MULU.L - 5
MULS.W - 2
MULS.L - 5
MULU/U.L - 6
MULS/U.L - 6
CLRMAC 1 1
LDMAC 1 1
STMAC 2 1
MAC 4 4
Instruction H8S H8SX
DIVXU.B 12 10
DIVU.W - 10
DIVXU.W 20 18
DIVU.L - 18
DIVXS.B 13 12
DIVS.W - 11
DIVXS.W 21 20
DIVS.L - 19
H8 Family CPU Core Overview
Advanced Multiplier
execution cycles
Advanced Divider
execution cycles
The H8 Architecture
7
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