Renesas User System Interface Board HS7047ECH61H Manuale Utente Pagina 46

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26
PE17
PE (21:18), PE (16:14),
PE (12:0)
PE (21:18), PE (16:14),
PE (12:0)
PF (15:0), PG (3:0) PF (15:0), PG (3:0)
SN74S1053NS
PE17
VHC244
PVcc
User systemMCU in the emulator
47 kΩ
Figure 3.8 User System Interface Circuits (6)
3.3.2 Delay Time with the User System Interface
The delay time is generated on the timing of the _RES signal when it is input to the MCU from the user system,
as shown in table 3.3, because this connection for this signal is via logic circuit on the evaluation chip board.
Table 3.3 Delay Time for Signal Connected via the Evaluation Chip Board
Signal Name Delay Time (ns)
_RES 15.0
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