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M16C/30P Group 1. Overview

Rev.1.22 Mar 30, 2007 Page 3 of 53

REJ03B0088-0122

1.3 Block Diagram

Figure 1.1 is a M16C/30P Group Block Diagram.

Figure 1.1 M16C/30P Group Block Diagram

Output (timer A): 3

Input (timer B): 3

Internal peripheral functions

Watchdog timer

(15 bits)

DMAC

(2 channels)

Memory

ROM

(1)

RAM

(2)

A/D converter

(10 bits X 18 channels)

UART or

clock synchronous serial I/O

(3 channels)

System clock

generation circuit

XIN-XOUT

XCIN-XCOUT

M16C/60 series16-bit CPU core

Port P0

8

Port P1

8

Port P2

8 8 8 8

Port P6

8

8

R0LR0H

R1H R1L

R2

R3

A0

A1

FB

SB

ISP

USP

INTB

CRC arithmetic circuit (CCITT )

(Polynomial : X

16

+X

12

+X

5

+1)

Multiplier

7 8 8

Port P10

Port P9Port P8_5Port P8Port P7

NOTES :

1. ROM size depends on microcomputer type.

2. RAM size depends on microcomputer type.

Port P5

Port P4Port P3

PC

FLG

Timer (16-bit)

1 2 3 4 5 6 7 8 9 10 ... 58 59

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