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SH7145 Group

SCI Break Detection

REJ06B0384-0100Z/Rev.1.00 September 2004 Page 4 of 20

• In asynchronous mode, serial data communication is performed with synchronization in character units, allowing

serial communication with a dedicated asynchronous communication LSI conforming to the Universal

Asynchronous Receiver/Transmitter (UART), Asynchronous Communication Interface Adapter (ACIA) or other

standard. Further, in asynchronous mode, a function (multiprocessor communication function) is provided for serial

communications with multiple processors.

• The internal peripheral clock Pφ is a reference clock used to drive the on-chip peripheral functions, and is generated

by the clock pulse generator.

• The receive shift register (RSR_0) is a register used to receive serial data. Serial data is input from the RxD0 pin,

and when data for one frame has been received, the data in RSR_0 is automatically transferred to the receive data

• The receive data register (RDR_0) is an 8-bit register used to store received data. Upon receiving data for one frame,

the data is automatically transferred from RSR_0. RSR_0 and RDR_0 have a double-buffered structure, so that

continuous receive operation is possible. Since RDR_0 is a receive-only register, only reading is possible from the

CPU.

• The transmit shift register (TSR_0) is a register used to transmit serial data. During transmission, data is transmitted

from the transmit data register (TDR_0) to TSR_0, and the transmission data is output from the TxD0 pin. TSR_0

cannot be directly accessed from the CPU.

• The transmit data register (TDR_0) is an 8-bit register used to store data for transmission. When TSR_0 is detected

to be empty, data written to TDR_0 is automatically transferred to TSR_0. TDR_0 and TSR_0 have a double-

buffered structure, so that when data for one frame has been transmitted and the next data is written to TDR_0, the

data is transferred to TSR_0. Continuous transmission is thus possible. TDR can always be read and written by the

CPU, but writing should be performed after confirming that the TDRE bit of the serial status register (SSR_0) is 1.

• The serial mode register (SMR_0) is an 8-bit register used to select the serial data communication format and the

clock source for the internal baud rate generator.

• The serial control register (SCR_0) is a register used to control transmission/reception and interrupts and select the

transmission/reception clock source.

• The serial status register (SSR_0) consists of SCI0 status flags and transmission/reception multiprocessor bits.

TDRE, RDRF, ORER, PER, and FER can only be cleared.

• The serial direction control register (SDCR_0) is used to select LSB-first or MSB-first. In 8-bit length

communications, either LSB-first or MSB-first can be selected, but in 7-bit communications, LSB-first should be

selected.

• The bit rate register (BRR_0) is an 8-bit register used to adjust the bit rate. In the SCI, a baud rate generator is

provided independently for each channel, so that different bit rates can be set. For the relationship between the

setting values and the execution rate and other details, please refer to the hardware manual.

Table 2 shows the assignment of functions in this sample task.

Table 2 Assignment of Functions

Element Classification Description

TXD0 Pin Channel 0 transmission data output pin

RXD0 Pin Channel 0 reception data input pin

SMR_0 SCI0 Sets communication format to asynchronous mode.

SCR_0 SCI0 Enables reception.

SSR_0 SCI0 Status flags indicating the operation state of SCI0

SDCR_0 SCI0 Set to select LSB-first.

BRR_0 SCI0 Sets the communication bit rate.

TSR_0 SCI0 Register for serial data transmission

TDR_0 SCI0 Register for storing data for transmission

RSR_0 SCI0 Register for receiving serial data

RDR_0 SCI0 Register for storing received data

1 2 3 4 5 6 7 8 9 ... 19 20

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