Renesas PROM Programming Adapter PCA7435FPG02 Specifiche

7534 GroupSINGLE-CHIP 8-BIT CMOS MICROCOMPUTERREJ03B0099-0300Rev.3.00Oct 23, 2006Rev.3.00 Oct 23, 2006 page 1 of 53REJ03B0099-0300DESCRIPTIONThe

7534 GroupRev.3.00 Oct 23, 2006 page 10 of 53REJ03B0099-0300MemorySpecial function register (SFR) areaThe SFR area in the zero page contains con

7534 GroupRev.3.00 Oct 23, 2006 page 11 of 53REJ03B0099-0300Fig. 11 Memory map of special function register (SFR)0 0 0 01 60 0 0 11 60 0 0 21 6

7534 GroupRev.3.00 Oct 23, 2006 page 12 of 53REJ03B0099-0300I/O Ports[Direction registers] PiDThe I/O ports have direction registers which deter

7534 GroupRev.3.00 Oct 23, 2006 page 13 of 53REJ03B0099-0300Table 3 I/O port function tableNameI/O port P0I/O port P1I/O port P2I/O port P3I/O

7534 GroupRev.3.00 Oct 23, 2006 page 14 of 53REJ03B0099-0300Fig. 14 Block diagram of ports (1)Data bus +-(1) Port P0Data bus DirectionregisterP

7534 GroupRev.3.00 Oct 23, 2006 page 15 of 53REJ03B0099-0300Fig. 15 Block diagram of ports (2)(9) Ports P36, P37Data busPort latchPull-up contr

7534 GroupRev.3.00 Oct 23, 2006 page 16 of 53REJ03B0099-0300Interrupt operationUpon acceptance of an interrupt the following operations are auto

7534 GroupRev.3.00 Oct 23, 2006 page 17 of 53REJ03B0099-0300Fig. 16 Interrupt controlFig. 17 Structure of Interrupt-related registersInterrupt

7534 GroupRev.3.00 Oct 23, 2006 page 18 of 53REJ03B0099-0300Key Input Interrupt (Key-On Wake-Up)A key-on wake-up interrupt request is generated

7534 GroupRev.3.00 Oct 23, 2006 page 19 of 53REJ03B0099-0300TimersThe 7534 Group has 3 timers: timer X, timer 1 and timer 2.The division ratio o

7534 GroupRev.3.00 Oct 23, 2006 page 2 of 53REJ03B0099-0300PIN CONFIGURATION (TOP VIEW)Fig. 2 Pin configuration of M37534M4-XXXGPO u t l i n e

7534 GroupRev.3.00 Oct 23, 2006 page 20 of 53REJ03B0099-0300Fig. 21 Block diagram of timer X, timer 1 and timer 2Timer modepulse output modeQRTo

7534 GroupRev.3.00 Oct 23, 2006 page 21 of 53REJ03B0099-0300Fig. 22 Block diagram of UART serial I/OFig. 23 Operation of UART serial I/O functio

7534 GroupRev.3.00 Oct 23, 2006 page 22 of 53REJ03B0099-0300[Serial I/O1 control register] SIO1CONThe serial I/O1 control register consists of e

7534 GroupRev.3.00 Oct 23, 2006 page 23 of 53REJ03B0099-0300• Universal serial bus (USB) modeBy setting bits 7 and 6 of the serial I/O1 control

7534 GroupRev.3.00 Oct 23, 2006 page 24 of 53REJ03B0099-0300Fig. 27 Structure of serial I/O1-related registers (1)b7

7534 GroupRev.3.00 Oct 23, 2006 page 25 of 53REJ03B0099-0300Fig. 28 Structure of serial I/O1-related registers (2)Not used (return “1” when read

7534 GroupRev.3.00 Oct 23, 2006 page 26 of 53REJ03B0099-0300Fig. 29 Structure of serial I/O1-related registers (3)b 7

7534 GroupRev.3.00 Oct 23, 2006 page 27 of 53REJ03B0099-0300Fig. 30 Structure of serial I/O1-related registers (4)USB sequence bit initializatio

7534 GroupRev.3.00 Oct 23, 2006 page 28 of 53REJ03B0099-0300Fig. 31 Structure of serial I/O1-related registers (5)UART control register(UARTCON:

7534 GroupRev.3.00 Oct 23, 2006 page 29 of 53REJ03B0099-0300Note on using USB modeHandling of SE0 signal in program (at receiving)7534 group has

7534 GroupRev.3.00 Oct 23, 2006 page 3 of 53REJ03B0099-0300PIN CONFIGURATION (TOP VIEW)Fig. 3 Pin configuration of M37534RSS, M37534M4-XXXSP, M

7534 GroupRev.3.00 Oct 23, 2006 page 30 of 53REJ03B0099-0300●Serial I/O2The serial I/O2 function can be used only for clock synchronous se-rial

7534 GroupRev.3.00 Oct 23, 2006 page 31 of 53REJ03B0099-0300Serial I/O2 operationBy writing to the serial I/O2 register(address 003116) the seri

7534 GroupRev.3.00 Oct 23, 2006 page 32 of 53REJ03B0099-0300A/D ConverterThe functional blocks of the A/D converter are described below.[A/D con

7534 GroupRev.3.00 Oct 23, 2006 page 33 of 53REJ03B0099-0300Watchdog TimerThe watchdog timer gives a means for returning to a reset statuswhen t

7534 GroupRev.3.00 Oct 23, 2006 page 34 of 53REJ03B0099-0300Reset CircuitThe microcomputer is put into a reset status by holding the RESETpin at

7534 GroupRev.3.00 Oct 23, 2006 page 35 of 53REJ03B0099-0300Fig. 42 Internal status of microcomputer at resetS e r i a l I / O 1 c o n t r o

7534 GroupRev.3.00 Oct 23, 2006 page 36 of 53REJ03B0099-0300Fig. 43 External circuit of ceramic resonatorFig. 44 External clock input circuitFig

7534 GroupRev.3.00 Oct 23, 2006 page 37 of 53REJ03B0099-0300Fig. 46 Block diagram of system clock generating circuit (for ceramic resonator)SRQS

7534 GroupRev.3.00 Oct 23, 2006 page 38 of 53REJ03B0099-0300NOTES ON PROGRAMMINGProcessor Status RegisterThe contents of the processor status re

7534 GroupRev.3.00 Oct 23, 2006 page 39 of 53REJ03B0099-0300Note on A/D ConverterMethod to stabilize A/D Converter is described below.(a) A/D co

7534 GroupRev.3.00 Oct 23, 2006 page 4 of 53REJ03B0099-0300S I / O 1 ( 8 )U S B ( L S ) R A M R O MC P UAXYSP CHP

7534 GroupRev.3.00 Oct 23, 2006 page 40 of 53REJ03B0099-0300ROM PROGRAMMING METHODThe built-in PROM of the blank One Time PROM version can bere

7534 GroupRev.3.00 Oct 23, 2006 page 41 of 53REJ03B0099-0300ELECTRICAL CHARACTERISTICSAbsolute Maximum RatingsTable 7 Absolute maximum ratings–0

7534 GroupRev.3.00 Oct 23, 2006 page 42 of 53REJ03B0099-0300Recommended Operating ConditionsTable 8 Recommended operating conditions(VCC = 4.1 t

7534 GroupRev.3.00 Oct 23, 2006 page 43 of 53REJ03B0099-0300Electrical CharacteristicsTable 9 Electrical characteristics (1) (VCC = 4.1 to 5.5 V

7534 GroupRev.3.00 Oct 23, 2006 page 44 of 53REJ03B0099-0300ResolutionLinearity errorDifferential nonlinear errorZero transition voltageFull sca

7534 GroupRev.3.00 Oct 23, 2006 page 45 of 53REJ03B0099-0300Timing RequirementsTable 12 Timing requirements (VCC = 4.1 to 5.5 V, VSS = 0 V, Ta

7534 GroupRev.3.00 Oct 23, 2006 page 46 of 53REJ03B0099-0300Fig. 52 Timing chart0.2VCCtd(SCLK-SDATA)tf0.2VCC0.8VCC0.8VCCtrtsu(SDATA-SCLK)th(SCLK

7534 GroupRev.3.00 Oct 23, 2006 page 47 of 53REJ03B0099-0300Differences among 32-pin, 36-pin and 42-pinThe 7534 Group has three package types, a

7534 GroupRev.3.00 Oct 23, 2006 page 48 of 53REJ03B0099-0300Table 16 Differences among 32-pin, 36-pin and 42-pin (SFR)42-pin SDIPBit 7 not avail

7534 GroupRev.3.00 Oct 23, 2006 page 49 of 53REJ03B0099-0300Fig. 53 Handling of VCC, USBVREFOUT pins of M37534M4-XXXFP, M37534E8FPDescription su

7534 GroupRev.3.00 Oct 23, 2006 page 5 of 53REJ03B0099-0300S I / O 1 ( 8 )U S B ( L S ) R A M R O MC P UAXYSP CHP

7534 GroupRev.3.00 Oct 23, 2006 page 50 of 53REJ03B0099-0300Fig. 54 Handling of VCC, USBVREFOUT pins of M37534M4-XXXGPOutline PLQP0032GB-AP 07P

7534 GroupRev.3.00 Oct 23, 2006 page 51 of 53REJ03B0099-0300Fig. 55 Handling of VCC, USBVREFOUT pins of M37534E8SP, M37534M4-XXXSP, M37534RSSOut

7534 GroupRev.3.00 Oct 23, 2006 page 52 of 53REJ03B0099-0300PACKAGE OUTLINEPRSP0036GA-AyIndex mark1181936F*1*2*EHEDebpAcDetail FA2LA1INCLUDE TRI

7534 GroupRev.3.00 Oct 23, 2006 page 53 of 53REJ03B0099-0300PRDP0042BA-A*3*3*2*1SEATING PLANE2221142b2bpb3DeAL2A1EcNOTE)*2"1.2.INCLUDE TRIM

REVISION HISTORY 7534 Group DATA SHEETRev. Date DescriptionPage Summary(1/2)1.00 Jan. 18, 2000 First edition issued –1.10 Jun. 14, 2000 package typ

REVISION HISTORY 7534 Group DATA SHEETRev. Date DescriptionPage Summary(2/2)NOTES ON USE; Note on A/D Converter addedPACKAGE OUTLINE revised3951, 523.

Notes:1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use.

7534 GroupRev.3.00 Oct 23, 2006 page 6 of 53REJ03B0099-0300Fig. 6 Functional block diagram (PRDP0042BA-A package type)T i m e r 1 ( 8 )T i m

7534 GroupRev.3.00 Oct 23, 2006 page 7 of 53REJ03B0099-0300PIN DESCRIPTIONTable 1 Pin descriptionPinVcc, VssVREFUSBVREFOUTCNVssRESETP00–P07P10/

7534 GroupRev.3.00 Oct 23, 2006 page 8 of 53REJ03B0099-0300GROUP EXPANSIONRenesas expands the 7534 group as follow:Memory typeSupport for Mask R

7534 GroupRev.3.00 Oct 23, 2006 page 9 of 53REJ03B0099-0300FUNCTIONAL DESCRIPTIONCentral Processing Unit (CPU)The 7534 Group uses the standard 7