Renesas SH7781 manuali

Renesas SH7781 Manuale Utente (1692 pagine)

Marchio: Renesas | Categoria: Hardware | Dimensione: 7.73 MB |

Indice

Hardware Manual

Preface

Contents

REJ09B0261-0100

Section 1 Overview

1. Overview

1.2 Block Diagram

1.3 Pin Arrangement Table

PKG TOP VIEW

PKG BTM VIEW

2.1 Data Formats

2.2 Register Descriptions

2. Programming Model

2.2.4 Control Registers

(1) Status Register (SR)

2.3 Memory-Mapped Registers

2.5 Data Formats in Memory

2.6 Processing States

2.7 Usage Notes

Section 3 Instruction Set

3. Instruction Set

Rn + 1/2/4

GBR + R0

3.3 Instruction Set

Comparis

Section 4 Pipelining

4. Pipelining

100

4.2 Parallel-Executability

106

OR.B #imm,@(R0,GBR)

107

5.2 Register Descriptions

119

5. Exception Handling

121

Table 5.3 Exceptions

126

5.5 Exception Flow

128

5.7 Usage Notes

153

6.1 Features

155

6.2 Data Formats

156

6.3 Register Descriptions

161

6.4 Rounding

167

7.1 Overview of MMU

174

7.2 Register Descriptions

182

D, and WT are not supported

203

7.5 MMU Functions

207

LRUI — URB — URC SV — TI — AT

209

PTEH PTEL

210

7.6 MMU Exceptions

212

(write value should be 0

222

00000000 00000000

234

7.9 32-Bit Boot Function

237

7.10 Usage Notes

239

Section 8 Caches

241

8. Caches

242

8.2 Register Descriptions

245

8.3 Operand Cache Operation

252

*********

267

8.7 Store Queues

268

Section 9 On-Chip Memory

273

9. On-Chip Memory

274

9.2 Register Descriptions

276

Control Register (RAMCR)

277

9.3 Operation

286

9.5 Usage Notes

291

10.1 Features

293

10.2 Input/Output Pins

302

10.3 Register Descriptions

303

10.4 Interrupt Sources

354

10.5 Operation

367

8Bcyc +

372

10.7 Usage Notes

373

IRQ/IRL[7:0] pin functions

374

11.1 Features

377

11.2 Input/Output Pins

380

11.3 Overview of Areas

384

11.4 Register Descriptions

392

11.5 Operation

417

PCMCIA Interface

484

12.1 Features

487

12.2 Input/Output Pins

490

12.3 Data Alignment

495

Set to 32 Bits

500

Set to 16 Bits

503

Width Is 16 Bits

507

Width Is 32 Bits

508

12.4 Register Descriptions

509

BASFT0BASFT1

516

WRRD0WRRD1WRRD2WRRD3

525

RDWR0RDWR1RDWR2RDWR3

525

12.5 DBSC2 Operation

542

Connected)

552

Are Connected)

553

Figure 12.16 tWR

569

Figure 12.20 tRFC

573

13.1 Features

581

13. PCI Controller (PCIC)

582

REQ0/REQOUT

583

GNT0/GNTIN

583

13.2 Input/Output Pins

584

13.3 Register Descriptions

587

Specification Revision 1.1

616

13.3.3 PCI Local Registers

620

SH: R

636

SH: R/W

643

Coherency

654

13.4 Operation

660

(Non-Byte Swapping: TBS = 0)

667

(Byte Swapping: TBS = 1)

668

14.1 Features

695

SuperHyway bus

696

14.2 Input/Output Pins

697

• DMARS4

724

• DMARS5

724

• DMARS0

724

• DMARS1

725

• DMARS2

726

• DMARS3

727

14.4 Operation

731

14.5 DMAC Interrupt Sources

759

14.6 Usage Notes

760

15.1 Features

763

15.2 Input/Output Pins

766

15.3 Clock Operating Modes

767

15.4 Register Descriptions

769

CLKOUTENB

780

16.1 Features

789

16.2 Input/Output Pins

791

16.3 Register Descriptions

792

16.4 Operation

799

× 20 = 5.24 [ms]

803

× 20 = 21.46 [s]

803

Section 17 Power-Down Mode

811

17. Power-Down Mode

812

17.2 Input/Output Pins

813

17.3 Register Descriptions

813

17.4 Sleep Mode

823

17.5 Deep Sleep Mode

824

18.1 Features

829

Bus interface

830

18.2 Input/Output Pins

831

18.3 Register Descriptions

832

• TSTR0

834

• TSTR1

835

18. Timer Unit (TMU)

836

18.4 Operation

840

18.5 Interrupts

844

18.6 Usage Notes

845

19.1 Features

847

19. Display Unit (DU)

848

19.2 Input/Output Pins

850

19.3 Register Descriptions

851

19.4 Operation

960

8 bits/

961

• UYVY format

969

• YUYV format

969

Plane 1 (YC data)

978

Plane 2 (YC data)

978

Plane 3 (YC data)

978

19.5 Display Control

986

19.5.4 Color Detection

995

19.6 Power-Down Sequence

998

20.1 Features

999

20.2 GDTA Address Space

1003

20.3 Register Descriptions

1004

CL_ENDMC_ENDCL_ERRMC_ERR

1011

20.4 GDTA Operation

1043

(3) CL Processing Procedure

1047

Frame height

1050

≤ x ≤ 255)

1050

(2) MC Processing Procedure

1057

20.5 Interrupt Processing

1059

20.6 Data Alignment

1059

20.7 Usage Notes

1061

21.1 Features

1063

SCFRDRn (128 stages)

1065

SCFTDRn (128 stages)

1065

Figure 21.2 SCIF0_RTS Pin

1066

Figure 21.3 SCIF0_CTS Pin

1067

SCIFn_RXD

1069

Peripheral bus

1069

Serial receive data

1069

21.3 Register Descriptions

1070

Error (%) =

1091

- 1 × 100

1091

Pck × 10

1091

(N + 1) × B × 64 × 2

1091

21.4 Operation

1101

(1) Data Transfer Format

1105

21.6 Usage Notes

1126

22.1 Features

1129

22.2 Input/Output Pins

1131

22.3 Register Descriptions

1132

B'10 or B'11

1152

22.4 Operation

1158

(4) Reception in Slave Mode

1172

23.1 Features

1181

23.2 Input/Output Pins

1183

23.3 Register Descriptions

1183

Peripheral clock frequency

1187

Serial clock frequency =

1187

23.4 Operation

1195

24.1 Features

1201

Peripheral bus interface

1202

24.2 Input/Output Pins

1202

24.3 Register Descriptions

1203

FIFO_EMPTY 0 R FIFO Empty

1212

(1) INTCR0

1213

(2) INTCR1

1215

(3) INTCR2

1216

(1) INTSTR0

1217

(2) INTSTR1

1220

(3) INTSTR2

1222

RSPTYR registers

1230

(1) RSPR0 to RSPR16

1234

(2) RSPRD

1234

DMAEN SET2 SET1 SET0

1238

24.4 Operation

1239

(with Data Busy State)

1244

(Block Size > FIFO Size)

1248

(Multiple Block Transfer)

1249

(Stream Transfer)

1250

(Single Block Transfer)

1251

Len (1 + n (DTI))

1253

- Cap × n (FFI)

1253

Set the number of blocks

1254

(Block Size ≤ FIFO Size)

1259

FRDYI interrupt

1285

detected or DMA transfer

1285

25.1 Features

1293

Figure 25.1 Block Diagram

1294

25.2 Input/Output Pins

1295

25.3 Register Descriptions

1296

STARY STDRY

1312

25.5 Operation

1318

26.1 Features

1327

26.2 Input/Output Pins

1329

26.3 Register Descriptions

1330

CKDV2 CKDV1 CKDV0

1331

DWL0 SWL2 SWL1

1331

26.4 Operation

1344

SSI_SDATA

1350

26.5 Usage Note

1365

27.1 Features

1367

27.2 Input/Output Pins

1370

27.3 Register Descriptions

1372

• Command access mode

1379

• Sector access mode

1380

TREND TRSTRT

1393

27.4 Operation

1394

16 bytes)

1395

64 bytes)

1397

Expansion

1399

(1) Physical Sector

1399

27.6 Interrupt Processing

1406

27.7 DMA Transfer Settings

1406

28.1 Features

1407

Interrupt

1408

28.2 Register Descriptions

1412

28.3 Usage Example

1479

29.1 Features

1483

29.2 Register Descriptions

1485

• CBR1

1490

• CRR1

1494

• CAR0

1495

• CAR1

1495

• CAMR0

1496

• CAMR1

1497

29.3 Operation Description

1503

29.5 User Break Examples

1511

29.6 Usage Notes

1515

30.1 Features

1517

Pin multiplexer

1518

Shift register

1518

30.2 Input/Output Pins

1519

Clock Pulse Generator (CPG)

1520

30.3 Register Description

1521

30.4 Operation

1533

30.5 Usage Notes

1537

Section 31 Register List

1539

31. Register List

1540

32.2 DC Characteristics

1592

32.3 AC Characteristics

1597

CSnWCR.WTH = 001)

1621

MCK0, MCK1

1623

Figure 32.36 IRQOUT Timing

1628

32.3.11 GPIO Signal Timing

1637

Appendix

1657

B. Mode Pin Settings

1658

Table B.3 Endian

1659

Table B.4 Master/Slave

1659

Table B.5 Clock Input

1659

Table B.6 Bus Mode

1660

Table B.7 Boot Address Mode

1660

Table B.8 Mode Control

1660

Table B.9 Mode Control

1660

C. Pin Functions

1661

C.2 Handling of Unused Pins

1672

F. Product Lineup

1687

−40 to 85°C 436-pin BGA

1687

−20 to 85°C 436-pin BGA

1687

RENESAS SALES OFFICES

1690

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Renesas SH7781 manuali

Renesas SH7781 Manuale Utente (1692 pagine)

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